Part 10 DSP/FPGAs Behaving Irrationally.Part 11: Using -ve Latency DSP to Cancel Unwanted Delays (this final part).If you would like to discuss any of the issues covered in the series, I can be reached at or LinkedIn Many innovations added, especially in the self-test/analysis area. Updating an original Analog Devices Sharc design to a faster, moreĬapable floating-point Intel Cyclone V FPGA design has been achieved and Some exotic irrational transfer function synthesis. GUI design for initialization, operation and analysis to approaches for Selection, hardware design, floating-point FPGA/DSP algorithmĭevelopment, built-in signal generation, measurement & self-test, PC Technical aspects from concept, feedback control structures, technology Series of articles has described an instrumentation project in all its Unwanted Delays associated with a Sampled-Data SystemThis Interested in that aspect, more information can be found here.įig 1. That active Intellectual Property applies to these concepts, if you are Science fiction or broken physics but the arrangement as described hasīeen successfully implemented in both commercial and research projects. Negative latency DSP may sound like the stuff of Some applications demand zero-latency or zero unwanted latency
To such factors as Nyquist filtering, ADC acquisition, DSP/FPGAĪlgorithm computation time, DAC reconstruction and circuit propagation This final article in the series will look at -ve latency DSP and how itĬan be used to cancel the unwanted delays in sampled-data systems due
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